I. Field of the Invention
This invention relates to a signal processing system employing real-time hierarchial pyramid signal processing techniques for analyzing and/or synthesizing a sampled temporal signal which defines an information component having one or more dimensions. More particularly, the signal processing system of the present invention employs multiplexing to substantially reduce the amount of hardware required to implement such a signal processing system.
II. Description of the Prior Art
U.S. Pat. No. 4,674,125 issued June 16, 1987 to C. R. Carlson, J. H. Arbeiter, and R. F. Bessler; assigned to RCA Corporation; and entitled "Real-Time Hierarchal Pyramid Signal Processing Apparatus"discloses real-time hierarchal pyramid signal processing apparatus which employs pipe-line architecture for analyzing, in delayed real time, the frequency spectrum of an n-dimensional (where n is a given integer having a value of at least one) information component defined by a sampled temporal signal (such as the two-dimensional spatial frequency spectrum of a television image defined by a sampled video signal); and for synthesizing, in delayed real time, such a sampled temporal signal from the analyzed frequency spectrum thereof. In particular, the signal processing apparatus disclosed in the Carlson et al. patent is capable of implementing hierarchial pyramid algorithms, such as one developed by Dr. Peter J. Burt (hereinafter referred to as the "Burt Pyramid") by means which include a relatively large number of stages. Each stage includes a digital convolution filter-decimator and expander-interpolation filter, each of which operates on a stream of signal samples. As disclosed in this Carlson et al. patent, the total amount of hardware required for the structure of all of these stages is quite large and, hence, relatively expensive.
Reference is made to co-pending U.S. application Ser. No. 632,467, filed July 19, 1984, by Arbeiter and issued Sept. 15, 1987, as U.S. Pat. No. 4,694,413 entitled "Compact Structure Input-Weighted Multitap Digital Filers", which discloses filter structure that significantly recuces the amount of hardware required to implement each stage. However, this application does not disclose a technique for reducing the number of separate stages of the device required to implement that pyramid analyzer and/or synthesizer.
Reference is further made to pages 79-88 of the book Multirate Digital Signal Processing, by C. Rochiere et al., published by Prentice Hall, Inc., in 1983, which discusses the use of polyphase component filters for decimation and interpolation with integer changes in sampling rate.